Agilent Technologies 16700 SERIES LOGIC ANALYSIS SYSTEM 16700 Uživatelský manuál stáhnout pdf (Strana 3)

Once this setup is complete, you can

configure the probing and trigger

sequence as desired.

Our example is a state mode meas-

urement. The clock for the state

measurement must be the same clock

that is used for the ILA measure-

ment. The 16700 Series setup screen

should look similar to Figure 4. We

have combined two logic analyzer

pods to create a 32-bit label named

“Count”. An additional signal named

"agilent_corr_ref" is connected to the

"Clock" input of pod A2 (see Figure 5)

and is used as a data input to the

16700 Series system. This is the trig-

ger out signal from the FPGA and is

used to align the data sets generated

by the ILA and the 16752A. We will

discuss this signal later in this

product note.

Figure 4. Setup for state measurement with 8 K samples. The clock is source from pod A1.

Note that the memory depth is user

selectable, as is the actual clock

setup. The memory depth is further

determined by the model of logic

analysis module installed in the

16700 Series mainframe. In this case

we are using a 16752A module with a

32 M sample buffer, but we will use

only 8 K of the available memory. We

have connected the "Clock" probe of

pod A1 to the FPGA input clock and

are using it as our sample clock. This

is the same clock used for the ILA.

Figure 5. Pod setup using a 32-bit count and single bit for the synchronizing signal

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Agilent Technologies 16700 SERIES LOGIC ANALYSIS SYSTEM 16700 Uživatelský manuál Strana 3