Agilent Technologies J-BERT N4903B Uživatelský manuál stáhnout pdf (Strana 4)

J-BERT N4903B High-Performance Serial BERT

The J-BERT N4903B high-performance serial BERT provides the

most complete jitter tolerance test for embedded and forwarded

clock devices.

It is the ideal choice for R&D and validation teams characterizing

and stressing chips and transceiver modules that have serial I/O

ports up to 7 Gb/s, 12.5 Gb/s or even 14.2 Gb/s. It can

characterize a receiver’s jitter tolerance and is designed to prove

compliance to today’s most popular serial bus standards, such as:

• PCI Express

• SATA/SAS

• DisplayPort

• USB Super Speed

• MIPI M-PHY

• SD UHS-II

• Thunderbolt

• Fibre Channel

• QPI and other front-side buses

• Memory buses, such as fully buffered DIMM2

• Backplanes, such as CEI, IEEE, Infiniband

• 10 GbE/ XAUI

• XFP/XFI, SFP+

• 100 GbE (10x 10G or 4x 25G)

Accurate characterization is achieved with clean

Press the Jitter button to set all

jitter parameters you need

Touch screen control of

all J-BERT parameters

Remote operation via LAN, GPIB, USB2

or GUI control via built-in web server

signals from the pattern generator, which features exceptionally low

jitter and extremely fast transition times. Built-in and calibrated jitter

sources allow accurate jitter tolerance testing of receivers.

Test set-up is simplified significantly, because the J-BERT N4903B is

designed to match serial bus standards optimally. It offers: differential

I/Os, variable voltage levels on all signal outputs, built-in jitter and ISI,

pattern sequencer, reference clock outputs, tunable CDR, pattern cap-

ture and bit recovery mode to analyze clock-less and non-deterministic

patterns.

Faster test execution is possible with J-BERT’s automated jitter toler-

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Agilent Technologies J-BERT N4903B Uživatelský manuál Strana 4