Agilent Technologies N5980A Uživatelský manuál

Procházejte online nebo si stáhněte Uživatelský manuál pro Multimetry Agilent Technologies N5980A. Smartest Characterization and Compliance Agilent J Uživatelská příručka

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Automated jitter tolerance
compliance and characterization
Calibrated jitter composition
Integrated into one box
Compliant to latest serial bus
standards
Smartest Characterization and
Compliance
Key Capabilities:
Integrated and calibrated jitter sources: PJ, SJ, RJ,
BUJ, ISI and sinusoidal interference
Jitter tolerance testing: PCI Express
®
, SATA, Fibre
Channel, FB-DIMM, CEI, 10 GbE, XFP/XFI
Quick eye masks and BER contours
Bit recovery mode for analyzing undeterministic
patterns
SSC generation
CDR with tunable loop bandwidth for compliant
measurements for all data rates
Pattern sequencer and capture to simplify the
handling of complex data patterns
Subrate clock outputs
Pattern generator options
All options upgradable
Version 3.1
New: Fastest Jitter Tolerance Results
(SW 4.5)
New: Pattern Generator
(options G07 and G13)
Includes specifications for tunable CDR
(options CTR, UTR)
Agilent J-BERT N4903A
High-Performance Serial BERT
with Complete Jitter Tolerance
Testing
7 Gb/s and 12.5 Gb/s
Data Sheet
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Shrnutí obsahu

Strany 1 - Data Sheet

Automated jitter tolerance compliance and characterizationCalibrated jitter compositionIntegrated into one box Compliant to latest serial bus standard

Strany 2

Table 13: Specification for the clock inputFrequency range 150 MHz to 12.5 GHz(option C13)150 MHz to 7 GHz(option C07)Amplitude 100 mV to 1.2 VSampli

Strany 3 - Applications

Table 15: Specifications for tunable loop bandwidth (only foroption CTR, UTR)Tunable loop bandwidth 500 kHz to 12 MHz for data rates 1.46 Gb/s to 12.

Strany 4 - Jitter Tolerance Tests

12 J-BERT N4903A High-Performance Serial BERT Data SheetTable 16: Specifications for trigger outputClock divider 4, 8, 16 up to 11 Gb/s32, 40, 64, 128

Strany 5 - User Interface

=UIFigure 22: Periodic jitter maximum for datarates ~ 3.375 Gb/susing the 500 ps delay line.J-BERT N4903A High-Performance Serial BERT Data SheetPerio

Strany 6

BUJ calibration datarate for PRBS filtersetting PRBS generatorCEI 6G 1.1 Gb/s PRBS 29-1 100 MHzCEI 11G 2 Gb/s PRBS 211-1 200 MHzGaussian

Strany 7

Table 26: Specifications for sinusoidal interference (SI)Amplitude 1)0 to 400 mV common mode, single ended and differential (differential amplitude 0

Strany 8

J-BERT N4903A High-Performance Serial BERT Data SheetTable 27: General mainframe characteristicsFigure 28: Rear panel viewDisplay8" color LCD tou

Strany 9 - Patterns

J-BERT N4903A High-Performance Serial BERT Includes 5x 50 Ω SMA terminations, 6x adapter SMAfemale to 2.4 mm male, USB cable, commercial cali-bration

Strany 10 - Specifications-Error Detector

® PCI Express is a registered trademark of PCI-SIG.Remove all doubtOur repair and calibration services will get your equipment backto you, performing

Strany 11

J-BERT N4903A High-Performance Serial BERT Data SheetTable 1: Serial BERT applications and selection guideDevice under test Typical requirements Recom

Strany 12

Available J-BERT configurationsBERT pattern generator and error detector,including built-in CDRBERT 150 Mb/s to 12.5 Gb/s N4903A-C13BERT 150 Mb/s to

Strany 13

J-BERT N4903A High-Performance Serial BERT Data Sheet4Figure 1: Manual jitter composition. This allows a combinationof jitter types to be injected.Jit

Strany 14

J-BERT N4903A High-Performance Serial BERT Data SheetFigure 5: Spectral jitter decomposition for debugging jitter sources in a design.Figure 6: Eye co

Strany 15

Figure 8: Bit recovery mode for analyzing non-deterministic traffic.6 J-BERT N4903A High-Performance Serial BERT Data SheetBit recovery mode (option A

Strany 16 - Mainframe Characteristics

Table 2: Output characteristics for J-BERT N4903A generator. Alltiming parameters are measured at ECL levels.Range of operation 150 Mb/s to 12.5 Gb/s

Strany 17 - Order Instructions

Table 7: Specifications for subrate clock outputDivider factors n = 2,3…128Levels High: + 0.5 V Low: --0.5 V typicalTransition times 35 ps typicalInte

Strany 18 - Related Literature Pub. No

Table 10: Specifications for auxiliary inputLevels TTL compatibleInterface DC coupled, 50 Ω nominalConnector SMA femaleJ-BERT N4903A High-Performance

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