
N4962A System Overview
Serial BERT 12.5 Gb/s User Guide 21
2.2 Rear Panel Quick Reference
Figure 4. N4962A rear panel
¯¯¯¯¯¯ , DataThru (SMA) – connected to IN¯¯, IN when ‘thru’ data path
– PRBS pattern trigger output
– PRBS generator clock input (default connected to TX CKO)
– error detector clock input (default connected to RX CKO)
– internal clock output for error detector
– internal clock output for PRBS generator
– high-frequency (9.85 – 11.35 GHz) clock output
– low-frequency (616 – 709 MHz) clock output
– low-frequency (616 – 709 MHz) clock input; used to phase
lock with external clock source
– jitter signal input (DC-100 MHz); turn jitter mode on before use
– GPIB connector, conforms to IEEE 488.1 mechanical specification
– N4962A serial number
– N4962A GPIB address (down is ‘0’, up is ‘1’, LSB is on
(Default GPIB address as shipped from the factory is 25)
– N4962A is powered when switch is toggled up towards
– connects with AC/DC adapter. Use only the supplied
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