Agilent Technologies N4962A Uživatelská příručka stáhnout pdf (Strana 30)

System Details and Performance Specifications

Serial BERT 12.5 Gb/s User Guide

Figure 7. N4962A block diagram – error detector

The error detector compares the sampled input bit stream to a separate

internal PRBS signal generated with the same configuration settings as the

PRBS generator. The error detector automatically synchronizes its internal

PRBS with the incoming bit stream, in a process called ‘training’. The error

detector is in training mode when off, and switches to error-counting mode

when the detector is turned on. Assuming the training was successful, and the

error detector was able to synchronize with the input bit stream, the detector

starts counting errors less than 1us after turning on.

Training the error detector takes approximately 50 us, and requires a somewhat

error-free input bit stream. If the detector is unable to synchronize with the

incoming bit stream, the measured BER will be very high. This is only an issue

for bit error rates higher than 5E-01 (50% of incoming bits are errors); for most

applications with high BER, the detector will auto-synchronize very rapidly.

The phase adjustment offers 2 degree resolution capability from 5 Gb/s to

12.5 Gb/s. The linearity accuracy of phase is limited to 10 degree steps for

operation from 5 Gb/s to 12.5 Gb/s. For external clock rates below 5 GHz the

specific values of 0, 90, 180 or 270 degrees are required for the receiver clock

phase alignment in order to obtain correct BER results. Employing the

receiver’s auto-phase feature or manual adjustment to the receiver phase

resulting in any other phase values may lead to receive errors. Users requiring

greater precision in receiver clock and data alignment below 5 GHz can achieve

this result using external means such as a mechanical phase-shifter.

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Agilent Technologies N4962A Uživatelská příručka Strana 30