Agilent Technologies ESG Specifikace Strana 199

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Fully Coded 3GPP W-CDMA Personality Users and Programming Guide 3-67
ESG Family Signal Generators Softkey Reference
Option 200 T
Timing Offset (numeric value) chip
This key enables you to specify the number of chips to be delayed in
addition to the slot delay between the downlink frame clock and uplink
frame timing signals. The actual delay time is the sum of 1024 chips,
the slot delay, and the timing offset.
Range:
512 to 2560 chips
Default: 0
Softkey Location (Uplink):
Mode > CDMA > W-CDMA > Link Up >
Uplink Sync Setup > Timing Offset (numeric value) chip
Total Bits
This field displays the actual number of total bits after the error bits
are inserted into the current data of each transport channel. This data
field is on the second page of the table editor.
Data Field Location (Uplink):
Mode > CDMA > W-CDMA > Link Up >
Link Control > 2 > Config Transport > Transport Channel # 1 to 6 >
TrCH Setup > Total Bit
Total Blocks
This field displays the actual number of total blocks after the error
blocks are inserted into the current data of each transport channel.
This data field is on the second page of the table editor.
Data Field Location (Uplink):
Mode > CDMA > W-CDMA > Link Up >
Link Control > 2 > Config Transport > Transport Channel # 1 to 6 >
TrCH Setup > Total Block
TPC Pat Steps
This field displays the number of successive down and up commands for
the transport power control (TPC) pattern, when the TPC Pattern field
is set to Up/Down or Down/Up. The power of the user equipment (UE) or
the base station (BS) will decrease or increase by 1 dB on a slot-by-slot
basis for every down or up command. For uplink, the TPC pattern has a
number of different formats. For downlink, the pattern is limited to
four formats. Press the
Edit Item key to select the TPC pattern steps.
Range: 1 to 80
Default: 1
Data Field Location (Downlink):
Mode > CDMA > W-CDMA >
Link Control > PhyCH Type > DPCH > PhyCH Setup > TPC Pat Steps
Data Field Location (Uplink):
Mode > CDMA > W-CDMA > Link Up >
Link Control > 1 > PhyCH Type > DPCCH > PhyCH Setup > TPC Pat Steps
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