Agilent Technologies ESG Specifikace Strana 270

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5-32 Fully Coded 3GPP W-CDMA Personality User’s and Programming Guide
Remote Programming and Examples ESG Family Signal Generators
W-CDMA Subsystem SCPI Command Reference Option 200
Uplink Synchronization Setup
Frame Clock Interval
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:FCLock:INTerval
FCL10|FCL20|FCL40|FCL80
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:FCLock:INTerval?
This command sets the frame clock interval for the uplink synchronization source.
FCL10 10 milliseconds
FCL20 20 milliseconds
FCL40 40 milliseconds
FCL80 80 milliseconds
*RST: FCL80
Frame Clock Polarity
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:FCLock:POLarity POSitive|NEGative
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:FCLock:POLarity?
This command sets the operating state of the frame clock for the uplink synchronization
source. The choices are either positive edge or negative edge.
*RST: Positive
SFN Reset Polarity
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:SFNRst:POLarity POSitive|NEGative
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:SFNRst:POLarity?
This command sets the operating state of the system frame number (SFN) reset signal for
the uplink synchronization. The choices are positive edge or negative edge.
*RST: Positive
Slot Delay Control
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:SDELay <0 to 119>
[:SOURce]:RADio:WCDMa:TGPP[:BBG]:ULINk:SDELay?
This command sets the number of slots to be delayed from the synchronization source. The
actual timing offset is (T0) + (Timeslot Delay) + (Timing Offset) where T0 (= 1024 chips) is
the standard timing offset between downlink and uplink.
Range: 0 to 119 slots
*RST: 0
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